85 search results - page 3 / 17 » Modeling and analysis of core-centric network processors |
SAC
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
INFOCOM
1993
IEEE
13 years 11 months ago
1993
IEEE
Worst-casebounds on delay and backlog are derived for leaky bucket constrained sessions in arbitrary topology networks of Generalized Processor Sharing (GPS) 10] servers. The inhe...