1617 search results - page 275 / 324 » Modeling and evaluation of hardware software designs |
152
Voted
ISPDC
2010
IEEE
15 years 3 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
176
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ICCAD
2002
IEEE
16 years 1 months ago
2002
IEEE
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
138
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ASPLOS
2010
ACM
15 years 11 months ago
2010
ACM
Contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past...
213
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FPGA
2006
ACM
15 years 8 months ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
145
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...