1205 search results - page 218 / 241 » Modeling organizational performance indicators |
168
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MICRO
2009
IEEE
16 years 14 days ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
153
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CODES
2008
IEEE
16 years 9 days ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
141
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DATE
2008
IEEE
16 years 9 days ago
2008
IEEE
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
156
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IJCNN
2008
IEEE
16 years 7 days ago
2008
IEEE
Abstract— Automatic pattern classifiers that allow for incremental learning can adapt internal class models efficiently in response to new information, without having to retrai...
178
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CODES
2007
IEEE
16 years 5 days ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...