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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 7 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
IPPS
1998
IEEE
14 years 2 months ago
Runtime Support for Virtual BSP Computer
Abstract. Several computing environments including wide area networks and nondedicated networks of workstations are characterized by frequent unavailability of the participating ma...
Mohan V. Nibhanupudi, Boleslaw K. Szymanski
ENTCS
2008
91views more  ENTCS 2008»
13 years 10 months ago
Expressing Priorities and External Probabilities in Process Algebra via Mixed Open/Closed Systems
Defining operational semantics for a process algebra is often based either on labeled transition systems that account for interaction with a context or on the so-called reduction ...
Mario Bravetti
IJCV
2006
121views more  IJCV 2006»
13 years 10 months ago
Feature-Based Sequence-to-Sequence Matching
This paper studies the problem of matching two unsynchronized video sequences of the same dynamic scene, recorded by different stationary uncalibrated video cameras. The matching i...
Yaron Caspi, Denis Simakov, Michal Irani
CVPR
2009
IEEE
1962views Computer Vision» more  CVPR 2009»
15 years 4 months ago
Histograms of Oriented Optical Flow and Binet-Cauchy Kernels on Nonlinear Dynamical Systems for the Recognition of Human Actions
System theoretic approaches to action recognition model the dynamics of a scene with linear dynamical systems (LDSs) and perform classification using metrics on the space of LDSs, ...
Rizwan Chaudhry, Avinash Ravichandran, Gregory D. ...