145 search results - page 4 / 29 » Modeling the Function Cache for Worst-Case Execution Time An... |
BIRTHDAY
2006
Springer
13 years 11 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
ISOLA
2010
Springer
13 years 6 months ago
2010
Springer
In object oriented languages, dynamic memory allocation is a fundamental concept. When using such a language in hard real-time systems, it becomes important to bound both the worst...
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
OTM
2004
Springer
14 years 29 days ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...