145 search results - page 9 / 29 » Modeling the Function Cache for Worst-Case Execution Time An... |
ISSS
2002
IEEE
14 years 17 days ago
2002
IEEE
Static timing analysis of embedded software is important for systems with hard real-time constraints. To accurately estimate time bounds, it is essential to model the underlying m...
ICCAD
2000
IEEE
14 years 1 days ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
ECRTS
2007
IEEE
14 years 2 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...