Sciweavers

805 search results - page 57 / 161
» Modeling the performance of algorithms on flash memory devic...
Sort
View
147
Voted
IPPS
2002
IEEE
15 years 9 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
142
Voted
IUI
2010
ACM
16 years 25 days ago
Haptic augmented reality dental trainer with automatic performance assessment
We developed an augmented reality (AR) dental training simulator utilizing a haptic (force feedback) device. A number of dental procedures such as crown preparation and opening ac...
Phattanapon Rhienmora, Kugamoorthy Gajananan, Pete...
ICS
2010
Tsinghua U.
15 years 8 months ago
Memory Consistency Conditions for Self-Assembly Programming
: Perhaps the two most significant theoretical questions about the programming of self-assembling agents are: (1) necessary and sufficient conditions to produce a unique terminal a...
Aaron Sterling
IPPS
2009
IEEE
15 years 10 months ago
Designing multi-leader-based Allgather algorithms for multi-core clusters
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
Krishna Chaitanya Kandalla, Hari Subramoni, Gopala...
116
Voted
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 8 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...