222 search results - page 42 / 45 » Modeling transactional memory workload performance |
SIGMETRICS
2006
ACM
14 years 2 months ago
2006
ACM
Understanding and managing the response time of web services is of key importance as dependence on the World Wide Web continues to grow. We present Remote Latency-based Management...
IPPS
2000
IEEE
14 years 29 days ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...