38 search results - page 7 / 8 » Modeling wire delay, area, power, and performance in a simul... |
ICCD
2007
IEEE
14 years 7 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ISQED
2009
IEEE
14 years 5 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
MOBISYS
2006
ACM
14 years 10 months ago
2006
ACM
The majority of security schemes available for sensor networks assume deployment in areas without access to a wired infrastructure. More specifically, nodes in these networks are ...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
Wireless mesh networks recently emerge as a flexible, low-cost and multipurpose networking platform with wired infrastructure connected to the Internet. A critical issue in mesh ...