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» Modelling Digital Circuits Problems with Set Constraints
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ICIP
2004
IEEE
14 years 11 months ago
Robust ego-motion estimation and 3d model refinement using depth based parallax model
We present an iterative algorithm for robustly estimating the egomotion and refining and updating a coarse, noisy and partial depth map using a depth based parallax model and brig...
Amit K. Agrawal, Rama Chellappa
EPIA
1999
Springer
14 years 2 months ago
Combinatorial Optimization in OPL Studio
OPL is a modeling language for mathematical programming and combinatorial optimization problems. It is the first modeling language to combine high-level algebraic and set notation...
Pascal Van Hentenryck, Laurent Michel, Philippe La...
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 3 months ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck
ISIPTA
2003
IEEE
140views Mathematics» more  ISIPTA 2003»
14 years 3 months ago
A Second-Order Uncertainty Model of Independent Random Variables: An Example of the Stress-Strength Reliability
A second-order hierarchical uncertainty model of a system of independent random variables is studied in the paper. It is shown that the complex nonlinear optimization problem for ...
Lev V. Utkin
EH
1999
IEEE
351views Hardware» more  EH 1999»
14 years 2 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...