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» Modelling Immunological Memory
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2004
IEEE
14 years 22 days ago
Predicting memory-access cost based on data-access patterns
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...
Surendra Byna, Xian-He Sun, William Gropp, Rajeev ...
PODS
2007
ACM
108views Database» more  PODS 2007»
14 years 9 months ago
Machine models and lower bounds for query processing
This paper gives an overview of recent work on machine models for processing massive amounts of data. The main focus is on generalizations of the classical data stream model where...
Nicole Schweikardt
MTDT
2002
IEEE
108views Hardware» more  MTDT 2002»
14 years 1 months ago
A Fault Modeling Technique to Test Memory BIST Algorithms
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil ...
DAC
2011
ACM
12 years 8 months ago
Litmus tests for comparing memory consistency models: how long do they need to be?
Memory consistency litmus tests are small parallel programs that are designed to illustrate subtle differences between memory consistency models by exhibiting different outcomes...
Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 7 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...