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MTDT
2002
IEEE

A Fault Modeling Technique to Test Memory BIST Algorithms

14 years 4 months ago
A Fault Modeling Technique to Test Memory BIST Algorithms
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip self test logic. Therefore the BIST logic should be comprehensively validated before fabrication. The key to this achievement lies in a robust memory fault model. In this paper we propose a novel fault modeling technique. This technique can scale to emulate any kind of memory architecture currently in use. The memory architecture and the location of any fault that can occur in the cell array are represented in terms of equations. The technique applies these equations and calculates an address where the fault can be modeled.
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where MTDT
Authors Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla
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