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GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
14 years 3 months ago
A design kit for a fully working shared memory multiprocessor on FPGA
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 2 months ago
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas...
NPL
2006
115views more  NPL 2006»
13 years 9 months ago
An RCE-based Associative Memory with Application to Human Face Recognition
In this paper we construct an associative memory model based on the restricted Coulomb energy (RCE) network. We propose a simple architecture and training algorithm for this RCE-b...
Xiaoyan Mu, Mehmet Artiklar, Paul Watta, Mohamad H...
CORR
2006
Springer
98views Education» more  CORR 2006»
13 years 9 months ago
Reversal Complexity Revisited
We study a generalized version of reversal bounded Turing machines where, apart from several tapes on which the number of head reversals is bounded by r(n), there are several furth...
André Hernich, Nicole Schweikardt
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 9 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture