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ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
14 years 7 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
DIAGRAMS
2000
Springer
14 years 2 months ago
Capacity Limits in Diagrammatic Reasoning
This paper examines capacity limits in mental animation of static diagrams of mechanical systems and interprets these limits within current theories of working memory. I review emp...
Mary Hegarty
PE
2010
Springer
175views Optimization» more  PE 2010»
13 years 5 months ago
Generalized ERSS tree model: Revisiting working sets
Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem. Existing characterization studi...
Ricardo Koller, Akshat Verma, Raju Rangaswami
JPDC
2006
92views more  JPDC 2006»
13 years 10 months ago
A tight bound on remote reference time complexity of mutual exclusion in the read-modify-write model
In distributed shared memory multiprocessors, remote memory references generate processor-to-memory traffic, which may result in a bottleneck. It is therefore important to design ...
Sheng-Hsiung Chen, Ting-Lu Huang
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
14 years 4 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...