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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 9 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
CODES
2000
IEEE
15 years 9 months ago
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 8 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 8 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
UML
1999
Springer
15 years 8 months ago
Extending Architectural Representation in UML with View Integration
UML has established itself as the leading OO analysis and design methodology. Recently, it has also been increasingly used as a foundation for representing numerous (diagrammatic) ...
Alexander Egyed, Nenad Medvidovic