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» Modelling and Evaluating Real-Time Software Architectures
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VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 8 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
COMPSAC
2005
IEEE
14 years 1 months ago
An Empirical Performance Study for Validating a Performance Analysis Approach: PSIM
Performance analysis gains more attention in recent years by researchers who focus their study on the early software development stages to mitigate the risk of redesign as problem...
Jinchun Xia, Yujia Ge, Carl K. Chang
DATE
2005
IEEE
168views Hardware» more  DATE 2005»
14 years 1 months ago
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
ICSEA
2007
IEEE
14 years 1 months ago
An Access Control Metamodel for Web Service-Oriented Architecture
— With the mutual consent to use WSDL (Web Service Description Language) to describe web service interfaces and SOAP as the basic communication protocol, the cornerstone for web ...
Christian Emig, Frank Brandt, Sebastian Abeck, J&u...
CGO
2005
IEEE
14 years 1 months ago
A Progressive Register Allocator for Irregular Architectures
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
David Koes, Seth Copen Goldstein