Sciweavers

6229 search results - page 101 / 1246
» Models of Computation for Networks on Chip
Sort
View
CODES
2009
IEEE
14 years 3 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
NCA
1998
IEEE
13 years 8 months ago
A Neural Network Model of a Communication Network with Information Servers
This paper models information flow in a communication network. The network consists of nodes that communicate with each other, and information servers that have a predominantly o...
Philippe De Wilde
DSD
2006
IEEE
99views Hardware» more  DSD 2006»
14 years 20 days ago
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
Rikard Thid, Ingo Sander, Axel Jantsch
CODES
2010
IEEE
13 years 7 months ago
Exploring models of computation with ptolemy II
The Ptolemy project studies modeling, simulation, and design of concurrent, real-time, embedded systems. The focus is on assembly of concurrent components. The key underlying prin...
Christopher X. Brooks, Edward A. Lee, Stavros Trip...
AINA
2005
IEEE
14 years 2 months ago
A Practical Modelling Notation for Secure Distributed Computation
Mobile code computation has lead to a new paradigm of distributed computation. A mobile process can move from site to site and interact with the resources as a local process. To p...
Yih-Jiun Lee, Peter Henderson