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» Models of Computation for Networks on Chip
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DAC
2008
ACM
13 years 10 months ago
Protecting bus-based hardware IP by secret sharing
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
DSN
2004
IEEE
14 years 22 days ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
INFOCOM
2009
IEEE
14 years 3 months ago
A Queueing Model Framework of PCE-Based Inter-Area Path Computation
Abstract—Path computation elements (PCE’s) are used to compute end-to-end paths across multiple areas. Multiple PCE’s may be dedicated to each area to provide sufficient path...
Juanjuan Yu, Yue He, Kai Wu, Marco Tacca, Andrea F...
GECCO
2007
Springer
212views Optimization» more  GECCO 2007»
14 years 3 months ago
A developmental model of neural computation using cartesian genetic programming
The brain has long been seen as a powerful analogy from which novel computational techniques could be devised. However, most artificial neural network approaches have ignored the...
Gul Muhammad Khan, Julian F. Miller, David M. Hall...
DAC
2008
ACM
14 years 10 months ago
Concurrent topology and routing optimization in automotive network integration
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
Bardo Lang, Christian Haubelt, Jürgen Teich, ...