6229 search results - page 114 / 1246 » Models of Computation for Networks on Chip |
DSN
2005
IEEE
14 years 2 months ago
2005
IEEE
1 In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems’ depe...
COMPCON
1994
IEEE
14 years 1 months ago
1994
IEEE
A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work d...
DSN
2008
IEEE
13 years 10 months ago
2008
IEEE
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
IEEEHPCS
2010
13 years 7 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
AINA
2009
IEEE
14 years 3 months ago
2009
IEEE
—This paper makes two contributions towards the logical modelling of inhibition in metabolic networks. First it exposes the logical inconsistency of an existing state-of-the-art ...