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» Models of Computation for Networks on Chip
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SAMOS
2004
Springer
14 years 2 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
14 years 2 months ago
A continuous time markov decision process based on-chip buffer allocation methodology
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Dob...

Lecture Notes
773views
15 years 7 months ago
Computer Networking and Internet Protocols: A Comprehensive Introduction
The lecture notes cover the following topics, Fundamentals (OSI Reference Model, Coding, Ethernet), Data Link Control (Flow Control, Error Control, HDLC, PPP), Internet Protocol ...
Raj Jain
IPPS
2006
IEEE
14 years 3 months ago
Cooperative load balancing for a network of heterogeneous computers
In this paper we present a game theoretic approach to solve the static load balancing problem in a distributed system which consists of heterogeneous computers connected by a sing...
Satish Penmatsa, Anthony T. Chronopoulos
ISCA
2006
IEEE
120views Hardware» more  ISCA 2006»
14 years 3 months ago
Interconnection Networks for Scalable Quantum Computers
We show that the problem of communication in a quantum computer reduces to constructing reliable quantum channels by distributing high-fidelity EPR pairs. We develop analytical m...
Nemanja Isailovic, Yatish Patel, Mark Whitney, Joh...