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» Models of Computation for Networks on Chip
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VLSID
2009
IEEE
99views VLSI» more  VLSID 2009»
14 years 9 months ago
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afz...
ETS
2006
IEEE
108views Hardware» more  ETS 2006»
14 years 2 months ago
A DFT Architecture for Asynchronous Networks-on-Chip
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
Xuan-Tu Tran, Jean Durupt, François Bertran...
DAC
2008
ACM
13 years 10 months ago
Keeping hot chips cool: are IC thermal problems hot air?
level of accuracy in IC package abstraction (compact models) to ensure robust thermal design. An overarching goal must be to reduce power consumption per function through smart pro...
Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J...
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 9 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
PPL
2008
185views more  PPL 2008»
13 years 8 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...