6229 search results - page 37 / 1246 » Models of Computation for Networks on Chip |
IEEEPACT
2009
IEEE
14 years 3 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fa...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
IPPS
2003
IEEE
14 years 2 months ago
2003
IEEE
Expresso is an experiment management system that is designed to assist biologists in planning, executing, and interpreting microarray experiments. It serves as a unifying framewor...
WS
2008
ACM
13 years 8 months ago
2008
ACM
This article presents the CHIP demonstrator5 for providing personalized access to digital museum collections. It consists of three main components: Art Recommender, Tour Wizard, an...