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» Models of Computation for Networks on Chip
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ACSD
2004
IEEE
124views Hardware» more  ACSD 2004»
14 years 17 days ago
A Behavioral Type Inference System for Compositional System-on-Chip Design
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc s...
Jean-Pierre Talpin, David Berner, Sandeep K. Shukl...
DAC
2001
ACM
14 years 9 months ago
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design
Communication-based design represents a formal approach to systemon-a-chip design that considers communication between components as important as the computations they perform. Ou...
Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Ke...
HPCC
2005
Springer
14 years 2 months ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
ISCAS
2006
IEEE
109views Hardware» more  ISCAS 2006»
14 years 2 months ago
Network-on-chip quality-of-service through multiprotocol label switching
Abstract— Providing Quality-of-Service (QoS) in networks-onchip (NoCs) will be an important consideration for the complex multiprocessor chips of the future. In this paper, we di...
Manho Kim, Daewook Kim, Gerald E. Sobelman
DAC
2002
ACM
14 years 9 months ago
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...