6229 search results - page 84 / 1246 » Models of Computation for Networks on Chip |
ICASSP
2009
IEEE
13 years 6 months ago
2009
IEEE
We have developed a VLSI chip for 5,000 word speakerindependent continuous speech recognition. This chip employs a context-dependent HMM (hidden Markov model) based speech recogni...
NOCS
2009
IEEE
14 years 3 months ago
2009
IEEE
Current Virtual-Channel routers disregard potentially useful information about on-chip communication flows. This often leads to inefficient resource utilisation in existing Netwo...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper? provides a description of our Network Time Interface M-Module NTI supporting high-accuracy external clock synchronization by hardware. The NTI is built around our custo...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
ANCS
2007
ACM
14 years 28 days ago
2007
ACM
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...