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» Models of Computation for Networks on Chip
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NOCS
2009
IEEE
14 years 3 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
NOCS
2007
IEEE
14 years 3 months ago
NoC-Based FPGA: Architecture and Routing
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
Roman Gindin, Israel Cidon, Idit Keidar
ISPASS
2009
IEEE
14 years 3 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ESANN
2008
13 years 10 months ago
Neural networks for computational neuroscience
Computational neuroscience is an appealing interdisciplinary domain, at the interface between biology and computer science. It aims at understanding the experimental data obtained...
David Meunier, Hélène Paugam-Moisy
IJON
2007
83views more  IJON 2007»
13 years 8 months ago
Neurospaces: Towards automated model partitioning for parallel computers
Parallel computers have the computing power needed to simulate biologically accurate neuronal network models. Partitioning is the process of cutting a model in pieces and assignin...
Hugo Cornelis, Erik De Schutter