NoC-Based FPGA: Architecture and Routing

We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instances with good performance and low cost. Our architecture minimizes the cost of supporting a wide range of design instances with given throughput requirements by balancing the amount of efficient hardcoded NoC infrastructure and the allocation of “soft” networking resources at configuration time. Although traffic patterns are design-specific, the physical link infrastructure is a performance bottleneck, and hence should be hard-coded. It is therefore important to employ routing schemes that allow for high flexibility to efficiently accommodate different traffic patterns during configuration. We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes. We propose a new routing scheme, Weighted Ordered Toggle (WOT), and sho...

• Type: Conference
• Year: 2007
• Where: NOCS
• Authors: Roman Gindin, Israel Cidon, Idit Keidar
• Keywords: Computer Networks, Design Instances, NOCS 2007, Routing Scheme, Traffic Patterns