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VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 1 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
DATE
2008
IEEE
66views Hardware» more  DATE 2008»
14 years 2 months ago
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
Tomokazu Yoneda, Hideo Fujiwara
DAC
2006
ACM
14 years 9 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
COGSCI
2011
49views more  COGSCI 2011»
13 years 3 months ago
What a Rational Parser Would Do
This article examines cognitive process models of human sentence comprehension based on the idea of informed search. These models are rational in the sense that they strive to qui...
John T. Hale
SCESM
2006
ACM
257views Algorithms» more  SCESM 2006»
14 years 2 months ago
Test ready UML statechart models
The dynamic behavior of systems is best described by Finite-state machines. Generation of executable tests from behavioral models such as UML Statecharts offers benefits such as s...
P. V. R. Murthy, P. C. Anitha, M. Mahesh, Rajesh S...