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135
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CODES
2007
IEEE
15 years 10 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
138
Voted
CODES
2007
IEEE
15 years 10 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
LCTRTS
2007
Springer
15 years 10 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
MIDDLEWARE
2007
Springer
15 years 10 months ago
CAESAR: middleware for complex service-oriented peer-to-peer applications
Recent research advances in Peer-to-Peer (P2P) computing have enabled the P2P paradigm to be used for developing complex applications beyond file sharing and data storage. These ...
Lipo Chan, Shanika Karunasekera, Aaron Harwood, Eg...
146
Voted
CODES
2006
IEEE
15 years 9 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
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