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IPPS
2006
IEEE
15 years 10 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
IPPS
2006
IEEE
15 years 10 months ago
Performance Analysis of the Reactor Pattern in Network Services
The growing reliance on services provided by software applications places a high premium on the reliable and efficient operation of these applications. A number of these applicat...
Swapna S. Gokhale, Aniruddha S. Gokhale, Jeffrey G...
ASPLOS
2006
ACM
15 years 10 months ago
Manitou: a layer-below approach to fighting malware
Unbeknownst to many computer users, their machines are running malware. Others are aware that strange software inhabits their machine, but cannot get rid of it. In this paper, we ...
Lionel Litty, David Lie
ISSTA
2006
ACM
15 years 10 months ago
Architecture-driven platform independent deterministic replay for distributed hard real-time systems
Distributed hard real-time systems have become a major component of many advanced technical products. Means to ensure their proper quality are thus of paramount importance. To ens...
Holger Giese, Stefan Henkler
MMSEC
2006
ACM
132views Multimedia» more  MMSEC 2006»
15 years 10 months ago
On achievable security levels for lattice data hiding in the known message attack scenario
This paper presents a theoretical security analysis of lattice data hiding. The security depends on the secrecy of a dither signal that randomizes the codebook. If the same secret...
Luis Pérez-Freire, Fernando Pérez-Go...