Sciweavers

77 search results - page 12 / 16
» Modifying Min-Cut for Hardware and Software Functional Parti...
Sort
View
ECBS
2007
IEEE
97views Hardware» more  ECBS 2007»
14 years 1 months ago
A Service-Oriented Extension of the V-Modell XT
The ever growing size and complexity of both technical and business systems requires efficient software engineering approaches to keep development cost under control while still ...
Michael Meisinger, Ingolf Krüger
APCCAS
2006
IEEE
224views Hardware» more  APCCAS 2006»
14 years 1 months ago
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding
We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance...
Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-We...
ERSA
2006
282views Hardware» more  ERSA 2006»
13 years 8 months ago
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santam...
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
14 years 2 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 19 days ago
Run-Time Management of Logic Resources on Reconfigurable Systems
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...