As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk ...
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
We present a new particle tracing approach for the simulation of mid- and high-frequency sound. Inspired by the photorealism obtained by methods like photon mapping, we develop a ...
Martin Bertram, Eduard Deines, Jan Mohring, Jevgen...
We present a method that computes a global potentially visible set for the complete region outside the convex hull of an object. The technique is used to remove invisible parts (t...