575 search results - page 111 / 115 » Multi-Valued Logic Synthesis |
ICCAD
2009
IEEE
13 years 7 months ago
2009
IEEE
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond...
ICCAD
2005
IEEE
14 years 6 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
FPGA
2010
ACM
14 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...