575 search results - page 63 / 115 » Multi-Valued Logic Synthesis |
GLVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
The ability of logic transformations to enhance safety property checking has been well-established, and many industrial-strength verification solutions accordingly rely ariety of...
CODES
2003
IEEE
14 years 3 months ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
FPL
2005
Springer
14 years 3 months ago
2005
Springer
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
AHS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...