575 search results - page 80 / 115 » Multi-Valued Logic Synthesis |
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
ERSA
2004
13 years 11 months ago
2004
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
ICCAD
2010
IEEE
13 years 7 months ago
2010
IEEE
Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negat...
ISCA
1999
IEEE
14 years 2 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
DLOG
2006
13 years 11 months ago
2006
Abstract. Modern description logic (DL) reasoners are known to be less efficient for DLs with inverse roles. The current loss of performance is largely due to the missing applicabi...