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DATE
2006
IEEE
112views Hardware» more  DATE 2006»
14 years 3 months ago
Automating processor customisation: optimised memory access and resource sharing
We propose a novel methodology to generate Application Specific Instruction Processors (ASIPs) including custom instructions. Our implementation balances performance and area req...
Robert G. Dimond, Oskar Mencer, Wayne Luk
ISCAS
2006
IEEE
94views Hardware» more  ISCAS 2006»
14 years 3 months ago
On the sensitivity of BDDs with respect to path-related objective functions
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...
Rüdiger Ebendt, Rolf Drechsler
ASPDAC
2006
ACM
114views Hardware» more  ASPDAC 2006»
14 years 3 months ago
High level equivalence symmetric input identification
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...
Ming-Hong Su, Chun-Yao Wang
ACSD
2005
IEEE
162views Hardware» more  ACSD 2005»
14 years 3 months ago
Complexity Results for Checking Distributed Implementability
We consider the distributed implementability problem as: Given a labeled transition system TS together with a distribution ∆ of its actions over a set of processes, does there ex...
Keijo Heljanko, Alin Stefanescu
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
14 years 3 months ago
Energy Bounds for Fault-Tolerant Nanoscale Designs
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
Diana Marculescu