575 search results - page 94 / 115 » Multi-Valued Logic Synthesis |
FPL
2009
Springer
14 years 2 months ago
2009
Springer
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
DATE
1999
IEEE
14 years 2 months ago
1999
IEEE
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
ISSS
1998
IEEE
14 years 2 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
ICCAD
1994
IEEE
14 years 2 months ago
1994
IEEE
We study a new placement problem: the reproducing placement problem (RPP). In each phase a module (or gate) is decomposed into two (or more) simpler modules. The goal is nd a \go...
CF
2004
ACM
14 years 1 months ago
2004
ACM
In this paper we present a novel methodology for partial (re-)configuration that can be used for most bitstream configured hardware (HW). In particular low priced and not for part...