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TON
2008
75views more  TON 2008»
13 years 6 months ago
TVA: a DoS-limiting network architecture
We motivate the capability approach to network denial-of-service (DoS) attacks, and evaluate the TVA architecture which builds on capabilities. With our approach, rather than send ...
Xiaowei Yang, David Wetherall, Thomas E. Anderson
CODES
2004
IEEE
13 years 10 months ago
Multi-objective mapping for mesh-based NoC architectures
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ISCAS
2005
IEEE
113views Hardware» more  ISCAS 2005»
14 years 9 days ago
Effect of traffic localization on energy dissipation in NoC-based interconnect
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend of SoC design. Scaleable communication-centric interconnect fabrics such as networks-onchip (No...
Partha Pratim Pande, Cristian Grecu, Michael Jones...
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 10 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
ICC
2007
IEEE
138views Communications» more  ICC 2007»
14 years 1 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi