Sciweavers

294 search results - page 30 / 59
» Multi-level customization in application engineering
Sort
View
CODES
2006
IEEE
14 years 1 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
IPPS
2000
IEEE
13 years 12 months ago
PaDDMAS: Parallel and Distributed Data Mining Application Suite
Discovering complex associations, anomalies and patterns in distributed data sets is gaining popularity in a range of scientific, medical and business applications. Various algor...
Omer F. Rana, David W. Walker, Maozhen Li, Steven ...
FCCM
1998
IEEE
169views VLSI» more  FCCM 1998»
13 years 11 months ago
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
Abstract Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing ...
Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohe...
LPNMR
2009
Springer
14 years 2 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
TEI
2012
ACM
258views Hardware» more  TEI 2012»
12 years 3 months ago
The HapticTouch toolkit: enabling exploration of haptic interactions
In the real world, touch based interaction relies on haptic feedback (e.g., grasping objects, feeling textures). Unfortunately, such feedback is absent in current tabletop systems...
David Ledo, Miguel A. Nacenta, Nicolai Marquardt, ...