5 search results - page 1 / 1 » Multi-level reconfigurable architectures in the switch model |
JSA
2010
13 years 5 months ago
2010
In this paper we study multi-level dynamically reconfigurable architectures. These are extensions of standard reconfigurable architectures where ordinary reconfiguration operation...
IPPS
1999
IEEE
14 years 3 months ago
1999
IEEE
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
DFT
1994
IEEE
14 years 3 months ago
1994
IEEE
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
HPCA
2006
IEEE
14 years 11 months ago
2006
IEEE
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
ERSA
2010
13 years 9 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...