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ARITH
2009
IEEE
14 years 2 months ago
Multi-operand Floating-Point Addition
The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored in this work. In particular, a 3-input FP adder is discussed in more d...
Alexandre F. Tenca
ARITH
2007
IEEE
14 years 2 months ago
Decimal Floating-Point Multiplication Via Carry-Save Addition
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This p...
Mark A. Erle, Michael J. Schulte, Brian J. Hickman...
ARITH
1999
IEEE
14 years 22 hour ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ARITH
2007
IEEE
14 years 2 months ago
Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations
The draft revision of the IEEE Standard for FloatingPoint Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP s...
Merav Aharoni, Ron Maharik, Abraham Ziv
ARITH
2009
IEEE
14 years 2 months ago
Energy and Delay Improvement via Decimal Floating Point Units
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiplyad...
Hossam A. H. Fahmy, Ramy Raafat, Amira M. Abdel-Ma...