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FPL
2004
Springer
112views Hardware» more  FPL 2004»
14 years 27 days ago
Automating the Layout of Reconfigurable Subsystems via Template Reduction
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
Shawn Phillips, Akshay Sharma, Scott Hauck
DEXAW
2004
IEEE
133views Database» more  DEXAW 2004»
13 years 11 months ago
ADUS: Indirect Generation of User Interfaces on Wireless Devices
Nowadays, there exists a great interest in wireless and mobile devices. However, the development of graphical user interfaces (GUIs) for applications in these environments must co...
Nikola Mitrovic, José A. Royo, Eduardo Mena
FPGA
1999
ACM
130views FPGA» more  FPGA 1999»
13 years 11 months ago
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition...
Frank Heile, Andrew Leaver
FCCM
1999
IEEE
134views VLSI» more  FCCM 1999»
13 years 11 months ago
Runlength Compression Techniques for FPGA Configurations
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
Scott Hauck, William D. Wilson
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
14 years 1 months ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...