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SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
14 years 4 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
CODES
2002
IEEE
14 years 3 months ago
Symbolic model checking of Dual Transition Petri Nets
This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models [12], using model checking techniques. The methodology presented a...
Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejand...
DATE
1999
IEEE
76views Hardware» more  DATE 1999»
14 years 3 months ago
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM...
Michel Renovell, Jean Michel Portal, Joan Figueras...
APL
1993
ACM
14 years 3 months ago
Array Morphology
Array morphology is the study of the form, structure, and evolution of arrays. An array annotation for a program written in an applicative array lanan abstract syntax tree for the...
Robert Bernecky
STACS
1992
Springer
14 years 2 months ago
A Simplified Technique for Hidden-Line Elimination in Terrains
In this paper we give a practical and e cient output-sensitive algorithm for constructing the display of a polyhedral terrain. It runs in Od + nlog2 n time and uses On n space, wh...
Franco P. Preparata, Jeffrey Scott Vitter