106 search results - page 6 / 22 » Multiple Branch and Block Prediction |
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardwa...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
ICPP
2002
IEEE
14 years 14 days ago
2002
IEEE
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
MICRO
1999
IEEE
13 years 11 months ago
1999
IEEE
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...