234 search results - page 5 / 47 » Multiple Faults: Modeling, Simulation and Test |
JUCS
2008
13 years 7 months ago
2008
: This paper presents efficient methods for online fault detection and diagnosis of Network-on-Chip (NoC) switches. The fault model considered in this research is a system level fa...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
ITC
2002
IEEE
14 years 20 days ago
2002
IEEE
The advantage to “one test at a time” fault diagnosis is its ability to implicate the components of complicated defect behaviors. The disadvantage is the large size and opacit...
DFT
1999
IEEE
14 years 1 days ago
1999
IEEE
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...
ITC
1994
IEEE
13 years 12 months ago
1994
IEEE
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...