234 search results - page 6 / 47 » Multiple Faults: Modeling, Simulation and Test |
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
ICONIP
2007
13 years 10 months ago
2007
Abstract. In neural networks, network faults can be exhibited in different forms, such as node fault and weight fault. One kind of weight faults is due to the hardware or software ...
ITC
1995
IEEE
14 years 15 days ago
1995
IEEE
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
EURODAC
1995
IEEE
14 years 16 days ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
ITC
2003
IEEE
14 years 2 months ago
2003
IEEE
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...