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HPCA
1995
IEEE
13 years 11 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
CASES
2001
ACM
13 years 11 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
IPPS
2003
IEEE
14 years 27 days ago
Multiple Instruction Stream Control for an Associative Model of Parallel Computation
This paper describes a system software design for multiple instruction stream control in a massively parallel associative computing environment. The purpose of providing multiple ...
Michael Scherger, Johnnie W. Baker, Jerry L. Potte...
DATE
2008
IEEE
171views Hardware» more  DATE 2008»
14 years 2 months ago
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
ASPLOS
2000
ACM
14 years 6 hour ago
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there ...
Allan Snavely, Dean M. Tullsen