377 search results - page 62 / 76 » Multiple Instruction Stream Processor |
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
ISLPED
2003
ACM
14 years 28 days ago
2003
ACM
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
PDPTA
2007
13 years 9 months ago
2007
- The MASC (for Multiple Associative Computing) model is a SIMD model enhanced with associative properties and multiple synchronous instruction streams (IS). A number of algorithms...