94 search results - page 10 / 19 » Multiple-banked register file architectures |
ARCS
1997
Springer
14 years 2 months ago
1997
Springer
The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by...
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
JSA
2006
13 years 10 months ago
2006
Interprocedural data flow analyses of executable programs suffer from the conservative assumptions that need to be made because no precise control flow graph is available and beca...
ICS
2007
Tsinghua U.
14 years 4 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
ISLPED
2006
ACM
14 years 4 months ago
2006
ACM
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...