94 search results - page 8 / 19 » Multiple-banked register file architectures |
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading)...
IEEEPACT
2003
IEEE
14 years 1 months ago
2003
IEEE
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hol...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-p...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...