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RTSS
2009
IEEE
14 years 3 months ago
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Ab...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
14 years 2 months ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 3 months ago
Process Variation Aware Issue Queue Design
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
Raghavendra K, Madhu Mutyam
WSC
2007
13 years 11 months ago
Modeling the performance of low latency queueing for emergency telecommunications
Event simulation and analytic modeling are used to evaluate the performance of Low Latency Queueing (LLQ), a queueing discipline available in some Internet packet switching router...
Denise M. Bevilacqua Masi, Martin J. Fischer, Davi...
ICRA
2007
IEEE
139views Robotics» more  ICRA 2007»
14 years 2 months ago
Multi-Robot Formations based on the Queue-Formation Scheme with Limited Communications
— In this paper, we investigate the operation of the Queue-formation structure (or Q-structure) in multi-robot teams with limited communications. Information flow is divided int...
Cheng-Heng Fua, Shuzhi Sam Ge, Khac Duc Do, Khiang...